On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's auto-correlation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps.