300 mm wafer-level hybrid bonding for Cu/interlayer dielectric bonding in vacuum

被引：19

作者：

Fujino, Masahisa ^{[1
]}

Takahashi, Kenji ^{[1
]}

Araga, Yuuki ^{[1
]}

Kikuchi, Katsuya ^{[1
]}

机构：

[1] Natl Inst Adv Ind Sci & Technol, AIST Tsukuba Cent 1, Nanoelect Res Inst NeRI, Umezono 1-1-1, Tsukuba, Ibaraki 3058560, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2020年 / 59卷 / SB期

关键词：

SURFACE-ROUGHNESS; SILICON-WAFERS; ROOM;

D O I：

10.7567/1347-4065/ab4b2b

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Wafer bonding technology is one of the key technologies for high-density three-dimensional integration. We demonstrated 300 mm wafer-level hybrid bonding with Cu and an interlayer dielectric (ILD) layer with the design of 1 x 1 mu m(2) pads with 2 mu m pitch. In this sequence of the bonding process, the structure of Cu bonding pads was controlled to be precisely convex to the ILD layer by chemical-mechanical polishing. Then the bonding process was performed in vacuum. Lastly, the bonded wafers were annealed at 200 degrees C for the postannealing process. As a result, hybrid wafer bonding with few voids was successfully accomplished. (C) 2019 The Japan Society of Applied Physics

引用

收藏

页数：8

相关论文

共 33 条

[11] Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration [J].

Gagnard, Xavier ;

Mourier, Thierry .

MICROELECTRONIC ENGINEERING, 2010, 87 (03) :470-476

[12] The effect of surface roughness on direct wafer bonding [J].

Gui, C ;

Elwenspoek, M ;

Tas, N ;

Gardeniers, JGE .

JOURNAL OF APPLIED PHYSICS, 1999, 85 (10) :7448-7454

[13] Room temperature wafer level glass/glass bonding [J].

Howlader, MMR ;

Suehara, S ;

Suga, T .

SENSORS AND ACTUATORS A-PHYSICAL, 2006, 127 (01) :31-36

[14] Ultra-fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process [J].

Kim, Soon-Wook ;

Detalle, Mikael ;

Peng, Lan ;

Nolmans, Philip ;

Heylen, Nancy ;

Velenis, Dimitrios ;

Miller, Andy ;

Beyer, Gerald ;

Beyne, Eric .

2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, :1179-1185

[15] Wafer level encapsulation of microsystems using glass frit bonding [J].

Knechtel, R ;

Wiemer, M ;

Frömel, J .

MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2006, 12 (05) :468-472

[16] High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing [J].

Kurz, F. ;

Plach, T. ;

Suess, J. ;

Wagenleitner, T. ;

Zinner, D. ;

Rebhan, B. ;

Dragoi, V. .

SEMICONDUCTOR WAFER BONDING: SCIENCE, TECHNOLOGY AND APPLICATIONS 14, 2016, 75 (09) :345-353

[17] WAFER BONDING FOR SILICON-ON-INSULATOR TECHNOLOGIES [J].

LASKY, JB .

APPLIED PHYSICS LETTERS, 1986, 48 (01) :78-80

[18] Bridging the processor-memory performance gap with 3D IC technology [J].

Liu, CC ;

Ganusov, I ;

Burtscher, M ;

Tiwari, S .

IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06) :556-564

[19] Galvanic Corrosion Control in Chemical Mechanical Polishing of Cu Interconnects with Ruthenium Barrier Metal Film [J].

Maruyama, Koji ;

Shiohara, Morio ;

Yamada, Kouji ;

Kondo, Seiichi ;

Saito, Shuichi .

JAPANESE JOURNAL OF APPLIED PHYSICS, 2009, 48 (04)

[20] ROLE OF SURFACE-MORPHOLOGY IN WAFER BONDING [J].

MASZARA, WP ;

JIANG, BL ;

YAMADA, A ;

ROZGONYI, GA ;

BAUMGART, H ;

DEKOCK, AJR .

JOURNAL OF APPLIED PHYSICS, 1991, 69 (01) :257-260

← 1 2 3 4 →