A CMOS nested-chopper instrumentation amplifier with 100-nV offset

被引：135

作者：

Bakker, A ^{[1
]}

Thiele, K

Huijsing, JH

机构：

[1] Philips Semicond, Sunnyvale, CA 94088 USA

[2] Delft Univ Technol, DIMES, Elect Instrumentat Lab, NL-2600 AA Delft, Netherlands

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 12期

关键词：

chopper amplifiers; instrumentation amplifiers; low-offset amplifiers; offset cancellation techniques;

D O I：

10.1109/4.890300

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV/root Hz consuming a total supply current of 200 muA.

引用

页码：1877 / 1883

页数：7

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