Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs

被引:12
作者
Kranti, A
Chung, TM
Flandre, D
Raskin, JP
机构
[1] Univ Catholique Louvain, Microwave Lab, B-1348 Louvain, Belgium
[2] Univ Catholique Louvain, Microelect Lab, B-1348 Louvain, Belgium
关键词
D O I
10.1088/0268-1242/20/5/017
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we analyse for the first time the effectiveness of the quasi-double gate (QDG) method for performance prediction of short channel double gate (DG) silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) over the entire operating region. An analytical model has been developed to explain the abnormally low values (<< 60 mV/decade) of subthreshold slope that are obtained in QDG devices. We extract the low field mobility (mu(o)), subthreshold slope (S), threshold voltage (V-th), transconductance-to-drain current ratio (g(m)/I-ds) and peak transconductance (g(m))(max) in linear and saturation regions for deep. submicron QDG devices. We demonstrate that the QDG method can accurately predict g(m)/I-ds, (gm)max and mu(o) values for a deep submicron real DG device in the linear and strong inversion regions.
引用
收藏
页码:423 / 429
页数:7
相关论文
共 27 条
[1]   From SOI materials to innovative devices [J].
Allibert, F ;
Ernst, T ;
Pretet, J ;
Hefyene, N ;
Perret, C ;
Zaslavsky, A ;
Cristoloveanu, S .
SOLID-STATE ELECTRONICS, 2001, 45 (04) :559-566
[2]   DOUBLE-GATE SILICON-ON-INSULATOR TRANSISTOR WITH VOLUME INVERSION - A NEW DEVICE WITH GREATLY ENHANCED PERFORMANCE [J].
BALESTRA, F ;
CRISTOLOVEANU, S ;
BENACHIR, M ;
BRINI, J ;
ELEWA, T .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (09) :410-412
[3]   THRESHOLD VOLTAGE MODEL FOR DEEP-SUBMICROMETER FULLY DEPLETED SOI MOSFETS [J].
BANNA, SR ;
CHAN, PCH ;
KO, PK ;
NGUYEN, CT ;
CHAN, MS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (11) :1949-1955
[4]   Electron transport in a model Si transistor [J].
Banoo, K ;
Lundstrom, MS .
SOLID-STATE ELECTRONICS, 2000, 44 (09) :1689-1695
[5]   A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs [J].
Chen, Q ;
Agrawal, B ;
Meindl, JD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) :1086-1090
[6]   Silicon on insulator technologies and devices: from present to future [J].
Cristoloveanu, S .
SOLID-STATE ELECTRONICS, 2001, 45 (08) :1403-1411
[7]   High performance fully-depleted tri-gate CMOS transistors [J].
Doyle, BS ;
Datta, S ;
Doczy, M ;
Hareland, S ;
Jin, B ;
Kavalieros, J ;
Linton, T ;
Murthy, A ;
Rios, R ;
Chau, R .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (04) :263-265
[8]   Ultimately thin double-gate SOI MOSFETs [J].
Ernst, T ;
Cristoloveanu, S ;
Ghibaudo, G ;
Ouisse, T ;
Horiguchi, S ;
Ono, Y ;
Takahashi, Y ;
Murase, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) :830-838
[9]   Speed superiority of scaled double-gate CMOS [J].
Fossum, JG ;
Ge, LX ;
Chiang, MH .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (05) :808-811
[10]   Electron mobility in double gate silicon on insulator transistors:: Symmetric-gate versus asymmetric-gate configuration [J].
Gámiz, F ;
Roldán, JB ;
Godoy, A ;
Cartujo-Cassinello, P ;
Carceller, JE .
JOURNAL OF APPLIED PHYSICS, 2003, 94 (09) :5732-5741