An entropy-based learning hardware organization using FPGA

被引：1

作者：

Starzyk, J ^{[1
]}

Guo, YT ^{[1
]}

机构：

[1] Ohio Univ, Sch Elect Engn & Comp Sci, Athens, OH 45701 USA

来源：

PROCEEDINGS OF THE 33RD SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY | 2001年

关键词：

D O I：

10.1109/SSST.2001.918519

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a neural network model with entropy-based evaluator called EBE is proposed. An FPGA based design that implements the EBE model is presented. The PCI bus interface including DMA transfer is embedded into the design. 8-bit test data is fed into the design to verify the correctness of the algorithm and its FPGA implementation.

引用

页码：209 / 213

页数：5

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