A Low-Power High-Speed Hybrid Full Adder

In this paper we present a new hybrid FA design (mix of CMOS and pass transistor logic styles), which aims at achieving higher speed but keeping power dissipation low, and hence targeting low PDP. Our proposed FA and seven other existing FA designs are simulated in spice, using 45 nm low power model file, using standard test bed and test pattern (56 input transitions) [1, 2], and the simulation results of these eight designs are compared in terms of power dissipation, propagation delay and PDP. Simulation results proves that our proposed FA design has the lowest propagation delay and lowest PDP across the simulated supply voltage range and the frequency range.