X-compact: An efficient response compaction technique

被引:156
作者
Mitra, S [1 ]
Kim, KS [1 ]
机构
[1] Intel Corp, Sacramento, CA 95827 USA
关键词
built-in self-test (BIST); compaction; test compression; testing; X-compact;
D O I
10.1109/TCAD.2004.823341
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X's), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.
引用
收藏
页码:421 / 432
页数:12
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