Custom analog low power design: The problem of low voltage and mismatch

被引:34
作者
Steyaert, M
Peluso, V
Bastos, J
Kinget, P
Sansen, W
Leuven, KU
机构
来源
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1997年
关键词
D O I
10.1109/CICC.1997.606631
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The never ending story of technology trends towards smaller transistor dimensions have resulted to date in deep submicron transistors. The consequence is the down scaling of the power supply voltages, to date even lower than 2 V, with almost the same threshold voltages of the CMOS transistors. Those low voltages make that some widespread techniques such as switched-capacitors can not be implemented anymore. On the other hand custom integrated circuits require time after time higher speed, more accuracy and less power drain. In the first section the impact of mismatch or accuracy in analog circuits and the impact on power drain is discussed. Secondly in section two some fundamental limitations of analog integrated circuit design in the trade-off between speed, accuracy and power drain are analysed. In the third section the problem of very low voltage signal processing in switched-capacitor circuits is studied. Some solutions, such as the switched-opamp technique are presented, and the technique is demonstrated by the design of a very low power, low voltage sigma delta modulator, The design and the measurements of the 12 bit sigma delta AD converters running at 1.5 V power supply voltage and consuming less than 100 mu W in standard CMOS technology are finaly discussed.
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页码:285 / 292
页数:8
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