Point defect scattering in silicon nanowires

被引：0

作者：

Pecchia, Alessandro ^{[1
]}

Penazzi, Gabriele ^{[2
]}

机构：

[1] CNR, ISMN, Via Salaria,Km 29-300, I-00016 Monterotondo, Italy

[2] Univ Roma Tor Vergata, I-00133 Rome, Italy

来源：

2010 14TH INTERNATIONAL WORKSHOP ON COMPUTATIONAL ELECTRONICS (IWCE 2010) | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A semi-empirical tight-binding Hamiltonian based on density functional theory is used to study scattering of defects in H-passivated (110)SiNWs. The effect of surface dangling bonds and the presence of oxygen on the coherent transport is considered. The scattering at Si vacancies is also studied.

引用

页码：9 / 12

页数：4

共 9 条

[1] Magic structures of H-passivated 110 silicon nanowires [J].

Chan, TL ;

Ciobanu, CV ;

Chuang, FC ;

Lu, N ;

Wang, CZ ;

Ho, KM .

NANO LETTERS, 2006, 6 (02) :277-281

[2] High performance silicon nanowire field effect transistors [J].

Cui, Y ;

Zhong, ZH ;

Wang, DL ;

Wang, WU ;

Lieber, CM .

NANO LETTERS, 2003, 3 (02) :149-152

[3] Self-consistent-charge density-functional tight-binding method for simulations of complex materials properties [J].

Elstner, M ;

Porezag, D ;

Jungnickel, G ;

Elsner, J ;

Haugk, M ;

Frauenheim, T ;

Suhai, S ;

Seifert, G .

PHYSICAL REVIEW B, 1998, 58 (11) :7260-7268

[4] Asymmetric Doping in Silicon Nanostructures: The Impact of Surface Dangling Bonds [J].

Hong, Ki-Ha ;

Kim, Jongseob ;

Lee, Jung Hoon ;

Shin, Jaikwang ;

Chung, U-In .

NANO LETTERS, 2010, 10 (05) :1671-1676

[5] Design Space for Low Sensitivity to Size Variations in [110] PMOS Nanowire Devices: The Implications of Anisotropy in the Quantization Mass [J].

Neophytou, Neophytos ;

Klimeck, Gerhard .

NANO LETTERS, 2009, 9 (02) :623-630

[6] Non-equilibrium Green's functions in density functional tight binding: method and applications [J].

Pecchia, A. ;

Penazzi, G. ;

Salvucci, L. ;

Di Carlo, A. .

NEW JOURNAL OF PHYSICS, 2008, 10

[7] High-performance fully depleted silicon-nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices [J].

Singh, N. ;

Agarwal, A. ;

Bera, L. K. ;

Liow, T. Y. ;

Yang, R. ;

Rustagi, S. C. ;

Tung, C. H. ;

Kumar, R. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. -L. .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :383-386

[8]

YEO KH, 2006, IEDM

[9]

ZHUGE JEA, 2010, IEEE T NANOTECH, V9

← 1 →