Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effectivenumber- of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes 640 mu W from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.