Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

被引:33
作者
Liu, Shaolong [1 ,2 ]
Rabuske, Taimur [1 ]
Paramesh, Jeyanandh [2 ]
Pileggi, Lawrence [2 ]
Fernandes, Jorge [1 ]
机构
[1] Univ Lisbon, Inst Engn Sistemas & Comp Invest & Desenvolviment, Inst Super Tecn, P-1000029 Lisbon, Portugal
[2] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
基金
美国安德鲁·梅隆基金会;
关键词
SAR; ADC; loop-unrolled; linearity; multi-comparator; comparator offset; charge redistribution; high-speed; calibration; low-power; SINGLE-CHANNEL; APPROXIMATION; 6-BIT; CMOS;
D O I
10.1109/TCSI.2017.2723799
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effectivenumber- of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes 640 mu W from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.
引用
收藏
页码:458 / 470
页数:13
相关论文
共 36 条
  • [1] [Anonymous], 2012, 2012 ASIA PACIFIC PO
  • [2] [Anonymous], 1974, Introduction to the Theory of Statistics
  • [3] A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOS
    Cao, Zhiheng
    Yan, Shouli
    Li, Yunchu
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (03) : 862 - 873
  • [4] A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS
    Chen, Long
    Ragab, Kareem
    Tang, Xiyuan
    Song, Jeonggoo
    Sanyal, Arindam
    Sun, Nan
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (03) : 244 - 248
  • [5] A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
    Chen, Shuo-Wei Michael
    Brodersen, Robert W.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) : 2669 - 2680
  • [6] Approximated distributions of the weighted sum of correlated chi-squared random variables
    Chuang, Li-Ling
    Shih, Yu-Shan
    [J]. JOURNAL OF STATISTICAL PLANNING AND INFERENCE, 2012, 142 (02) : 457 - 472
  • [7] Chun-Cheng Liu, 2010, 2010 IEEE International Solid-State Circuits Conference (ISSCC), P386, DOI 10.1109/ISSCC.2010.5433970
  • [8] Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch
    Fredenburg, Jeffrey A.
    Flynn, Michael P.
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (07) : 1396 - 1408
  • [9] A 26 μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios
    Harpe, Pieter J. A.
    Zhou, Cui
    Bi, Yu
    van der Meijs, Nick P.
    Wang, Xiaoyan
    Philips, Kathleen
    Dolmans, Guido
    de Groot, Harmke
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (07) : 1585 - 1595
  • [10] An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit
    Jiang, Shan
    Do, Manh Anh
    Yeo, Kiat Seng
    Lim, Wei Meng
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (06) : 1430 - 1440