A Low-Power High-Speed Charge-Steering Comparator for High-Speed Applications

Comparators are essential blocks in implementing high speed flash ADCs. This paper introduces a low-power high-speed charge-steering comparator with off-chip clock calibration circuit. A prototype of the proposed comparator is implemented in 65-nm CMOS technology, where it consumes 80 mu W drawn from a 1.2 V supply while operating at 5 GHz. The low-power consumption is achieved by utilizing charge-steering concept, and operating on multiple clocks that minimize the overlapping operation period between the cascaded blocks of the implemented comparator.