Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

被引：8

作者：

Chiang, Kuan-Ying ^{[1
]}

Ho, Yu-Hao ^{[1
]}

Chen, Yo-Wei ^{[1
]}

Pan, Cheng-Sheng ^{[2
]}

Li, James Chien-Mo ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Lab Dependable Syst LaDS, Taipei, Taiwan

[2] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

来源：

2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS) | 2015年

关键词：

FinFET; ATPG; SDD;

D O I：

10.1109/ATS.2015.38

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

引用

页码：181 / 186

页数：6

共 23 条

[21] Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
Ghosh, I
Fujita, M
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (03) : 402 - 415
[22] Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
Hillebrecht, Stefan
Polian, Ilia
Engelke, Piet
Becker, Bernd
Keim, Martin
Cheng, Wu-Tung
2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 870 - +
[23] Performance Prediction for Multiple-Threshold 7nm-FinFET-Based Circuits Operating in Multiple Voltage Regimes Using a Cross-Layer Simulation Framework
Chen, Shuang
Wang, Yanzhi
Lin, Xue
Xie, Qing
Pedram, Massoud
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014,

← 1 2 3 →