Reconfigurable Intra Prediction Hardware for Future Video Coding

被引：9

作者：

Azgin, Hasan ^{[1
]}

Mert, Ahmet Can ^{[1
]}

Kalali, Ercan ^{[1
]}

Hamzaoglu, Ilker ^{[1
]}

机构：

[1] Sabanci Univ, Elect Engn Dept, TR-34956 Istanbul, Turkey

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 2017年 / 63卷 / 04期

关键词：

FVC; Intra Prediction; Reconfigurable Hardware; ENERGY REDUCTION TECHNIQUE; TRANSFORM HARDWARE; COMPUTATION;

D O I：

10.1109/TCE.2017.015118

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, two Future Video Coding (FVC) reconfigurable intra prediction hardware are proposed. They are the first FVC intra prediction hardware in the literature. The first hardware implements multiplications with constants using adders and shifters instead of using multipliers. Therefore, it can be used in ASIC implementations of FVC encoders. The second hardware implements multiplications with constants using DSP blocks in FPGA. Therefore, it can be used in FPGA implementations of FVC encoders.

引用

页码：419 / 425

页数：7

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