Ge-Source Based L-Shaped Tunnel Field Effect Transistor for Low Power Switching Application

被引:27
作者
Chander, Sweta [1 ]
Sinha, Sanjeet Kumar [1 ]
Chaudhary, Rekha [1 ]
Singh, Avtar [2 ]
机构
[1] Lovely Profess Univ, Sch Elect & Elect Engn, Phagwara, Punjab, India
[2] Adama Univ Sci & Technol, Dept ECE, Adama, Ethiopia
关键词
Tunnel field effect transistor; Heterojucntion; Band-to-band tunneling; Ambipolarity; Subthreshold swing; GATE; TFET; FET;
D O I
10.1007/s12633-021-01475-9
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
In this work, the performance of the heterojunction L-Tunnel Field Effect Transistor (LTFET) has been analyzed with different engineering techniques such as bandgap engineering, pocket engineering, work-function engineering, and gate dielectric engineering, respectively. The electrical characteristics of the device has been investigated by using Synopsys Sentaurus TCAD tool and compared with some recent other TFETs. The device has been analyzed in terms of DC as well as AC analysis and offers ON-state current of 2.12*10(-5) A mu m(-1), OFF-state current of 1.09*10(-13) A mu m(-1), current ratio of similar to 10(8) and sub-threshold slope (SS) of 21 mV/decade and the threshold voltage of 0.26 V and compared to the conventional Si/Ge source L-shaped TFETs without pocket simulation result. The pocket engineering techniques suppress the leakage without degrading the ON current, threshold voltage and SS of the proposed device. The simplified fabrication steps of the proposed device have also been discussed. The proposed L-TFET is free from ambipolarity issues and can be used to develop low-power switching devices.
引用
收藏
页码:7435 / 7448
页数:14
相关论文
共 33 条
[1]   Robust TFET SRAM cell for ultra-low power IoT applications [J].
Ahmad, Sayeed ;
Alam, Naushad ;
Hasan, Mohd .
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2018, 89 :70-76
[2]   Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric [J].
Anghel, Costin ;
Chilagani, Prathyusha ;
Amara, Amara ;
Vladimirescu, Andrei .
APPLIED PHYSICS LETTERS, 2010, 96 (12)
[3]   Technology for advanced high-performance microprocessors [J].
Bohr, MT ;
El-Mansy, YA .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (03) :620-625
[4]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[5]   Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs [J].
Chander, S. ;
Baishya, S. ;
Sinha, S. K. ;
Kumar, S. ;
Singh, P. K. ;
Baral, K. ;
Tripathy, M. R. ;
Singh, A. K. ;
Jit, S. .
SUPERLATTICES AND MICROSTRUCTURES, 2019, 131 :30-39
[6]   Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET [J].
Chander, Sweta ;
Sinha, Sanjeet Kumar ;
Kumar, Sanjay ;
Singh, Prince Kumar ;
Baral, Kamalaksha ;
Singh, Kunal ;
Jit, Satyabrat .
SUPERLATTICES AND MICROSTRUCTURES, 2017, 110 :162-170
[7]   Heterojunction fully depleted SOI-TFET with oxide/source overlap [J].
Chander, Sweta ;
Bhowmick, B. ;
Baishya, S. .
SUPERLATTICES AND MICROSTRUCTURES, 2015, 86 :43-50
[8]   Hetero-Gate-Dielectric Tunneling Field-Effect Transistors [J].
Choi, Woo Young ;
Lee, Woojun .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (09) :2317-2319
[9]   A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance [J].
Dash, S. ;
Mishra, G. P. .
ADVANCES IN NATURAL SCIENCES-NANOSCIENCE AND NANOTECHNOLOGY, 2015, 6 (03)
[10]  
Dewey G, 2011, P IEEE IEDM DEC, P1