Chip-to-chip communications using capacitive interconnects

被引：0
|
作者：
Viitala, Olli [1 ]
Ryynanen, Jussi [1 ]
机构：
[1] Aalto Univ, Dept Micro & Nanosci, FIN-00076 Aalto, Finland
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
LINK;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a transceiver for capacitive interconnects between two chips. The capacitive link model was simulated with an EM-simulator and a lumped circuit model was developed from the simulations. The channel model was then used in the design of the transceiver. The designed transceiver was implemented in 65-nm CMOS and the chip stack was assembled with standard equipment. The paper also presents the BER measurement results for the transceiver.
引用
收藏
页码：2888 / 2891
页数：4
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