DRAGO chip: A low-noise CMOS preamplifier shaper for silicon detectors with integrated front-end JFET

We present a CMOS preamplifier-shaper circuit designed to be used with low-noise solid-state detectors, like silicon drift detectors (SDDs), in X-ray Spectroscopy and gamma-ray imaging applications. The circuit is composed of a low-noise preamplifier and by a sixth-order semi-Gaussian shaping amplifier with four selectable peaking times from 1.7 mu s up to 6 mu s. The integrated time constants used for the shaping are implemented by means of a recently proposed "RC" cell. This cell is based on the demagnification of the current flowing in a resistor R thanks to the use of current mirrors. The particular solution adopted here allows a precise and stable implementation of the desired time constant, for given values of R and C, and guarantees low-noise performances of the shaping amplifier when used with a cooled SDDs or other solid-state detectors with low leakage current. In this work, the main features of the circuit are first presented. The experimental results obtained with a prototype realized in the 0.35-mu m 3.3-V CMOS austriarmcrosystems technology are then reported and discussed. The energy resolution measured using the chip with a SDD cooled at -10 degrees C is 150 eV at 6 keV which corresponds to an electronics noise of 10.8 e-rms.