Lowering STM Overhead with Static Analysis

被引:6
作者
Afek, Yehuda [1 ]
Korland, Guy [1 ]
Zilberstein, Arie [1 ]
机构
[1] Tel Aviv Univ, Dept Comp Sci, Tel Aviv, Israel
来源
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING | 2011年 / 6548卷
关键词
Transactional Memory; Optimization; Static Analysis; TRANSACTIONAL MEMORY; OPTIMIZATION;
D O I
10.1007/978-3-642-19595-2_3
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Software Transactional Memory (STM) compilers commonly instrument memory accesses by transforming them into calls to STM library functions. Done naively, this instrumentation imposes a large overhead, slowing down the transaction execution. Many compiler optimizations have been proposed in an attempt to lower tins overhead. In this paper we attempt to drive the STM overhead lower by discovering sources of sub-optimal instrumentation, and providing optimizations to eliminate them. The sources are: (1) redundant reads of memory locations that have been read before, (2) redundant writes to memory locations that will be subsequently written to, (3) redundant writeset lookups of memory locations that have not been written to, and (4) redundant writeset record-keeping for memory locations that will not be read. We describe how static analysis and code motion algorithms can detect these sources, and enable compile-time optimizations that significantly reduce the instrumentation overhead in many common cases. We implement the optimizations over a TL2 Java-based STM system, and demonstrate the effectiveness of the optimizations on various benchmarks, measuring up to 29-50% speedup in a single-threaded run, and up to 19% increased throughput in a 32-threads run.
引用
收藏
页码:31 / 45
页数:15
相关论文
共 28 条
[1]  
Adl-Tabatabai AR, 2006, ACM SIGPLAN NOTICES, V41, P26, DOI 10.1145/1133981.1133985
[2]  
Agrawal K., 2006, Proceedings of the 2006 workshop on Memory system performance and correctness, MSPC '06, (New York, NY, USA), P70
[3]   Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs [J].
Barik, Rajkishore ;
Sarkar, Vivek .
18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 2009, :41-52
[4]  
Beckman NelsE., 2009, INT WORKSHOP ALIASIN, P1, DOI http://doi.acm.org/10.1145/1562154.1562156
[5]   Subtleties of transactional memory atomicity semantics [J].
Department of Computer and Information Science, University of Pennsylvania, Philadelphia, PA, United States .
IEEE Comput. Archit. Lett., 2006, 2
[6]  
Bruneton Eric, 2002, P AD EXT COMP SYST
[7]   Software Transactional Memory: Why is it Only a Research Toy? [J].
Cascaval, Calin ;
Blundell, Colin ;
Michael, Maged ;
Cain, Harold W. ;
Wu, Peng ;
Chiras, Stefanie ;
Chatterjee, Siddhartha .
COMMUNICATIONS OF THE ACM, 2008, 51 (11) :40-46
[8]  
Cooper KD, 1997, ACM SIGPLAN NOTICES, V32, P308, DOI 10.1145/258916.258943
[9]  
Demsky B., 2010, 5 ACM SIGPLAN WORKSH
[10]  
Dice D, 2006, LECT NOTES COMPUT SC, V4167, P194