REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs

被引:64
作者
Ding, Caiwen [2 ]
Wang, Shuo [1 ]
Liu, Ning [2 ]
Xu, Kaidi [2 ]
Wang, Yanzhi [2 ]
Liang, Yun [1 ,3 ]
机构
[1] Peking Univ, Sch EECS, Ctr Energy Efficient Comp & Applicat CECA, Beijing, Peoples R China
[2] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA
[3] Peng Cheng Lab, Shenzhen, Peoples R China
来源
PROCEEDINGS OF THE 2019 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS (FPGA'19) | 2019年
基金
北京市自然科学基金; 美国国家科学基金会;
关键词
FPGA; YOLO; object detection; compression; ADMM; NETWORKS;
D O I
10.1145/3289602.3293904
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Deep neural networks (DNNs), as the basis of object detection, will play a key role in the development of future autonomous systems with full autonomy. The autonomous systems have special requirements of real-time, energy-efficient implementations of DNNs on a power-constrained system. Two research thrusts are dedicated to performance and energy efficiency enhancement of the inference phase of DNNs. The first one is model compression techniques while the second is efficient hardware implementation. Recent works on extremely-low-bit CNNs such as the binary neural network (BNN) and XNOR-Net replace the traditional floating point operations with binary bit operations which significantly reduces the memory bandwidth and storage requirement. However, it suffers from non-negligible accuracy loss and underutilized digital signal processing (DSP) blocks of FPGAs. To overcome these limitations, this paper proposes REQ-YOLO, a resource aware, systematic weight quantization framework for object detection, considering both algorithm and hardware resource aspects in object detection. We adopt the block-circulant matrix method and propose a heterogeneous weight quantization using Alternative Direction Method of Multipliers (ADMM), an effective optimization technique for general, non-convex optimization problems. To achieve real-time, highly-efficient implementations on FPGA, we present the detailed hardware implementation of block circulant matrices on CONV layers and develop an efficient processing element (PE) structure supporting the heterogeneous weight quantization, CONV dataflow and pipelining techniques, design optimization, and a template-based automatic synthesis framework to optimally exploit hardware resource. Experimental results show that our proposed REQ-YOLO framework can significantly compress the YOLO model while introducing very small accuracy degradation. The related codes are here: https://github.com/Anonymous788/heterogeneous_ADMM_YOLO.
引用
收藏
页码:33 / 42
页数:10
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