Power - Performance optimal 64-bit carry-lookahead adders

被引：16

作者：

Zlatanovici, R ^{[1
]}

Nikolic, B ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257137

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A circuit sizing tool that minimizes the delay under energy constraints has been developed using optimisation software, tabulated delay models and analytical energy models. The tool is used to generate energy-delay (E-D) tradeoff curves for selected high-performance 64-bit carry-lookahead domino adders. The optimisation indicates that the sparse radix-4 carry-lookahead adder with sparseness factor of 2 has optimal performance in the energy-delay space.

引用

页码：321 / 324

页数：4

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