Influence of accumulated charges on deep trench etch process in 3D NAND memory

被引：12

作者：

Han, Chen ^{[1
,2
,3
]}

Wu, Zhipeng ^{[3
]}

Yang, Chuan ^{[3
]}

Xie, Liuqun ^{[3
]}

Xu, Bo ^{[3
]}

Liu, Liheng ^{[3
]}

Yin, Zi ^{[3
]}

Jin, Lei ^{[1
,2
,3
]}

Huo, Zongliang ^{[1
,2
,3
]}

机构：

[1] Univ Chinese Acad Sci, Beijing 100049, Peoples R China

[2] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[3] Yangtze Memory Technol Co Ltd, Wuhan 430205, Peoples R China

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2020年 / 35卷 / 04期

关键词：

etch; word-line leakage; charges; CSL slit tilting; 3D NAND flash memory; HOLE;

D O I：

10.1088/1361-6641/ab73e7

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH etch process can affect the CSL slit etch process seriously, and lead to CSL tilting issue. Charging model was used to explain the phenomenon and is validated by experiments. An approach by removing the backside films for charges release via poly-Si deposition film is proposed to solve this issue. This work provides effective approach to solve the special deep trench tilting issue in 3D NAND memory processes development.

引用

页数：6

共 22 条

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