Automated hardware design using genetic programming, VHDL, and FPGAs

被引：0

作者：

Popp, RL ^{[1
]}

Montana, DJ ^{[1
]}

Gassner, RR ^{[1
]}

Vidaver, G ^{[1
]}

Iyer, S ^{[1
]}

机构：

[1] ALPHATECH Inc, Burlington, MA 01803 USA

来源：

1998 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-5 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this research we developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely, genetic programming (GP), VHSIC hardware description language (VHDL), and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist at this point in time. Other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date.

引用

页码：2184 / 2189

页数：6

共 50 条

[41] Neural network implementation in hardware using FPGAs
Sahin, Suhap
Becerikli, Yasar
Yazici, Suleyman
NEURAL INFORMATION PROCESSING, PT 3, PROCEEDINGS, 2006, 4234 : 1105 - 1112
[42] Hardware Trojan Detection using FBHT in FPGAs
Qayyum, Sundus
Qureshi, Kashif Naseer
Bashir, Faisal
Ul Islam, Najam
Malik, Nazir
PROCEEDINGS OF 2020 17TH INTERNATIONAL BHURBAN CONFERENCE ON APPLIED SCIENCES AND TECHNOLOGY (IBCAST), 2020, : 422 - 427
[43] Hardware accelerators for Cartesian genetic programming
Vasicek, Zdenek
Sekanina, Lukas
GENETIC PROGRAMMING, PROCEEDINGS, 2008, 4971 : 230 - +
[44] An efficient memory allocation algorithm and hardware design with VHDL synthesis
Karabiber, F.
Sertbas, A.
Ozdemir, S.
Cam, H.
INTERNATIONAL JOURNAL OF ELECTRONICS, 2008, 95 (02) : 125 - 138
[45] INTEGRATING SDL AND VHDL FOR SYSTEM-LEVEL HARDWARE DESIGN
GLUNZ, W
KRUSE, T
ROSSEL, T
MONJAU, D
COMPUTER HARDWARE DESCRIPTION LANGUAGES AND THEIR APPLICATIONS, 1993, 32 : 187 - 204
[46] Automatic Generation of Verified Concurrent Hardware Using VHDL
Silva, Luciano
Oliveira, Marcel
FORMAL METHODS: FOUNDATIONS AND APPLICATIONS, SBMF 2022, 2022, 13768 : 55 - 72
[47] Semantically Embedded Genetic Programming: Automated Design of Abstract Program Representations
Krawiec, Krzysztof
GECCO-2011: PROCEEDINGS OF THE 13TH ANNUAL GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE, 2011, : 1379 - 1386
[48] Compromise Rank Genetic Programming for Automated Nonlinear Design of Disaster Management
Wei, Shuang
Leung, Henry
MATHEMATICAL PROBLEMS IN ENGINEERING, 2015, 2015
[49] Multitask genetic programming for automated design of heuristics for the container relocation problem
Durasevic, Marko
Dumic, Mateja
Gala, Francisco Javier Gil
ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE, 2025, 144
[50] A Data Parallel Approach to Genetic Programming Using Programmable Graphics Hardware
Chitty, Darren M.
GECCO 2007: GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE, VOL 1 AND 2, 2007, : 1566 - 1573

← 1 2 3 4 5 →