Modeling within-Die spatial correlation effects for process-design co-optimization

被引：102

作者：

Friedberg, P ^{[1
]}

Cao, Y ^{[1
]}

Cain, J ^{[1
]}

Wang, R ^{[1
]}

Rabaey, J ^{[1
]}

Spanos, C ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISQED.2005.82

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Within-die spatial correlation of device parameter values caused by manufacturing variations [1] has a significant impact on circuit performance. Based on experimental and simulation results, we (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact on the variability of circuit performance.

引用

页码：516 / 521

页数：6

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