A hardware-efficient parallel architecture for real-time blob analysis based on run-length code

被引:4
作者
Li, Bingjie [1 ]
Zhang, Cunguang [1 ]
Li, Bo [1 ,2 ]
Jiang, Hongxu [1 ,2 ]
Xu, Qizhi [1 ,2 ]
机构
[1] Beihang Univ, Beijing Key Lab Digital Media, Sch Comp Sci & Engn, Beijing 100191, Peoples R China
[2] Beihang Univ, State Key Lab Virtual Real Technol & Syst, Beijing 100191, Peoples R China
基金
中国国家自然科学基金;
关键词
Blob analysis; Parallelization; Convex hull calculation; FPGA; COMPONENT LABELING ALGORITHM; CONNECTED-COMPONENT;
D O I
10.1007/s11554-017-0709-0
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Blob analysis has been extensively used in target detection, object recognition, moving target tracking, among other applications. Because blob analysis is computationally expensive, it has become a bottleneck of real-time applications. To tackle this problem, a parallel algorithm for blob analysis is proposed, and a hardware-efficient architecture for this algorithm is presented in this paper. First, based on image data partition and multi-process units, a novel parallel algorithm of blob analysis is proposed to process objects with different types and sizes. Second, a dynamic convex hull calculation method is designed, which is highly efficient for parallel processing and sub-block merging of connected component labeling. Third, a parallel hardware structure of the proposed algorithm is designed and implemented on FPGA. To evaluate performance, blobs of different types and sizes are located by the proposed algorithm in software and hardware. The experimental results demonstrate that the blobs are effectively and correctly located by the proposed algorithm, and the proposed hardware architecture works more efficiently than the state-of-the-art methods.
引用
收藏
页码:657 / 672
页数:16
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