Analysis and Modeling of a SAR-VCO Hybrid ADC Architecture

This paper presents a novel Nyquist SAR-VCO ADC architecture. To improve the dynamic performance, a 4-phase counter is introduced to the proposed architecture. Thanks to the employed 4-phase counter, requirements on both the counting time error and the nonlinearity of the VCO gain are relaxed. In addition, rather than adopting the oversampling strategy to realize the noise-shaping, the proposed Nyquist architecture can quantize signals at as high as the Nyquist frequency. Hence, the signal bandwidth is broadened successfully. Beyond these, influences of nonideal effects (such as linearity of the VCO gain, mismatch between the differential VCO gains, counting time error and clock jitter) from practical circuit implementations and layout designs are theoretically analyzed and modeled. Behavioral simulations show that, at the near Nyquist input frequency and 10 MS/s sampling rate, an SNDR of 61.43 dB, an SFDR of 78.08 dB and an ENOB of 9.91 bit are achieved, respectively.