Hardware friendly vector quantization algorithm

被引:8
|
作者
Matsubara, S [1 ]
Hikawa, H [1 ]
机构
[1] Oita Univ, Dept Comp Sci & Intelligent Syst, Oita 8701192, Japan
关键词
D O I
10.1109/ISCAS.2005.1465414
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a new vector quantization algorithm that can be directly implemented by hardware and its performance is discussed. The algorithm is based on the assumption that most of the vector elements in the same class fall within a certain range. Proposed algorithm provides very fast vector quantization with a dedicated hardware. VHDL simulations with real world data verify the feasibility of the system followed by the circuit size and speed evaluation. Results show that the proposed system has higher performance than those of K-nearest-neighbor method or neural network approach.
引用
收藏
页码:3623 / 3626
页数:4
相关论文
共 50 条
  • [1] A Method Supporting Hardware Implementation of Vector Quantization Module in HoG Algorithm
    Dlugosz, Zofia
    Talaska, Tomasz
    Dlugosz, Rafal
    2024 31ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MIXDES 2024, 2024, : 75 - 79
  • [2] Rough winner-take-all for hardware oriented vector quantization algorithm
    Tamukoh, Hakaru
    Horio, Keiichi
    Yamakawa, Takeshi
    Sekine, Masatoshi
    IEICE ELECTRONICS EXPRESS, 2011, 8 (11): : 773 - 779
  • [3] A Modified Parallel Learning Vector Quantization Algorithm for Real-Time Hardware Applications
    Alkim, Erdem
    Akleylek, Sedat
    Kilic, Erdal
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (10)
  • [4] Fast Parallel Memetic Algorithm for Vector Quantization Based for Reconfigurable Hardware and Softcore Processor
    Yu, Tsung-Yi
    Hwang, Wen-Jyi
    Chiang, Tsung-Che
    ADVANCES IN SWARM INTELLIGENCE, PT 1, PROCEEDINGS, 2010, 6145 : 479 - 488
  • [5] Modified vector quantization algorithm to overcome the blocking artefact problem of vector quantization algorithm
    Hasnat, Abul
    Barman, Dibyendu
    Halder, Santanu
    Bhattacharjee, Debotosh
    JOURNAL OF INTELLIGENT & FUZZY SYSTEMS, 2017, 32 (05) : 3711 - 3727
  • [6] Hardware Implementation of Multiple Vector Quantization Decoder
    Shigei, Noritaka
    Miyajima, Hiromi
    Hashiguchi, Shingo
    Maeda, Michiharu
    Ma, Lixin
    INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2008, 8 (11): : 54 - 61
  • [7] An improvement algorithm for vector quantization
    Aldavood, MM
    Tabatabaian, SJ
    8TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XII, PROCEEDINGS: APPLICATIONS OF CYBERNETICS AND INFORMATICS IN OPTICS, SIGNALS, SCIENCE AND ENGINEERING, 2004, : 270 - 273
  • [8] Hardware-friendly Deep Learning by Network Quantization and Binarization
    Qin, Haotong
    PROCEEDINGS OF THE THIRTIETH INTERNATIONAL JOINT CONFERENCE ON ARTIFICIAL INTELLIGENCE, IJCAI 2021, 2021, : 4911 - 4912
  • [9] Designing a hardware accelerator for vector quantization as a component of a SOPC
    Huynh, Thuan
    Cao, Thuong
    Tran, Diem
    Nguyen, Phuong
    Dinh, Anh
    2008 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-4, 2008, : 455 - 459
  • [10] Hardware Friendly Algorithm for Earthquakes Discrimination Based on Wavelet Filter Bank and Support Vector Machine
    Saad, Omar M.
    Shalaby, Ahmed
    Inoue, Koji
    Sayed, Mohammed S.
    2018 PROCEEDINGS OF THE INTERNATIONAL JAPAN-AFRICA CONFERENCE ON ELECTRONICS, COMMUNICATIONS, AND COMPUTATIONS (JAC-ECC 2018), 2018, : 115 - 118