Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking

被引：8

作者：

Derakhshandeh, Jaber ^{[1
]}

Beyne, Eric ^{[1
]}

Beyer, Gerald ^{[1
]}

Capuz, Giovanni ^{[1
]}

Cherman, Vladimir ^{[1
]}

De Preter, Inge ^{[1
]}

Gerets, Carine ^{[1
]}

Shafahian, Ehsan ^{[1
]}

Kennes, Koen ^{[1
]}

Jamieson, Geraldine ^{[1
]}

Cochet, Tom ^{[1
]}

Webers, Tomas ^{[1
]}

Tobback, Bert ^{[1
]}

Van der Plas, Geert ^{[1
]}

La Tulipe, Douglas Charles ^{[1
]}

Phommahaxay, Alain ^{[1
]}

Miller, Andy ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022) | 2022年

关键词：

TBM (temporary bonding material); TCB; Low temperature damascene processing on wafer BS; spacer and solder bumps; intermetallic compound; 3D die to wafer stacking; wafer to wafer bonding;

D O I：

10.1109/ECTC51906.2022.00179

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, for first time, damascene process on thinned and bonded device wafer to a carrier using TBM layer is introduced. All the BS process steps including, dielectric depositions, etching, seed/barrier deposition, plating and CMP are performed at temperatures within the thermal budget of TBM layer. FIB images show no impact of BS processing on FS bumps. This process is done on a test vehicle with 20, 10, 7 and 5um pitch structures in F2F and B2F (or F2B) forms, where good electrical data, good solder joint formation and good reliability performance is obtained.

引用

页码：1108 / 1113

页数：6

共 10 条

[1]

Beyne E., 2021, ISSCC

[2]

De preter Inge, 2016, ESTC

[3]

derakhshandeh J., 2019, IICT MAM

[4] 3D stacking using bump-less process for sub 10um pitch interconnects [J].

Derakhshandeh, Jaber ;

De Preter, Inge ;

Gerets, Carine ;

Hou, Lin ;

Heylen, Nancy ;

Beyne, Eric ;

Beyer, Gerald ;

Slabbekoorn, John ;

Dubey, Vikas ;

Jourdain, Anne ;

Potoms, Goedele ;

Inoue, Fumihiro ;

Jamieson, Geraldine ;

Vandersmissen, Kevin ;

Suhard, Samuel ;

Webers, Tomas ;

Capuz, Giovanni ;

Wang, Teng ;

Rebibis, Kenneth June ;

Miller, Andy .

2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, :128-133

[5]

derakhshandeh Jaber, 2020, ECTC

[6]

Gerber M, 2011, ELEC COMP C, P612, DOI 10.1109/ECTC.2011.5898576

[7]

Nagano Fuya, 2017, MAM

[8] Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips [J].

Samavedam, S. B. ;

Ryckaert, J. ;

Beyne, E. ;

Ronse, K. ;

Horiguchi, N. ;

Tokei, Z. ;

Radu, I ;

Bardon, M. G. ;

Na, M. H. ;

Spessot, A. ;

Biesemans, S. .

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,

[9] Transition from flip chip solder joint to 3D IC microbump: Its effect on microstructure anisotropy [J].

Tu, K. N. ;

Hsiao, Hsiang-Yao ;

Chen, Chih .

MICROELECTRONICS RELIABILITY, 2013, 53 (01) :2-6

[10]

Vakanas George, 2014, MAM

← 1 →