MiniBit: Bit-width optimization via affine arithmetic

被引：33

作者：

Lee, DU ^{[1
]}

Gaffar, AA ^{[1
]}

Mencer, O ^{[1
]}

Luk, W ^{[1
]}

机构：

[1] Univ London Imperial Coll Sci & Technol, Dept Comp, London, England

来源：

42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005 | 2005年

关键词：

affine arithmetic; bit-width; fixed-point; FPGA; simulated annealing;

D O I：

10.1109/DAC.2005.193931

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20% and 12% respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA.

引用

页码：837 / 840

页数：4

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