A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

被引：2

作者：

Reddy, Reeshen ^{[1
,2
]}

Sinha, Saurabh ^{[2
,3
]}

机构：

[1] CSIR, ZA-0184 Pretoria, South Africa

[2] Univ Pretoria, Dept Elect Elect & Comp Engn, Carl & Emily Fuchs Inst Microelect, ZA-0002 Pretoria, South Africa

[3] Univ Johannesburg, Fac Engn & Built Environm, ZA-2006 Auckland Pk, South Africa

来源：

MICROELECTRONICS JOURNAL | 2015年 / 46卷 / 04期

关键词：

Digital-analogue conversion; BiCMOS integrated circuits; Dynamic range; Analogue-digital integrated circuits; Mixed analogue digital integrated circuits; Wideband; CMOS; GHZ;

D O I：

10.1016/j.mejo.2015.02.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascade and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon-germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm(2) and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：310 / 319

页数：10

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