A low power 50 MHz FFT processor with cyclic extension and shaping filter

被引：2

作者：

Bickerstaff, M ^{[1
]}

Arivoli, T ^{[1
]}

Ryan, PJ ^{[1
]}

Weste, N ^{[1
]}

Skellern, D ^{[1
]}

机构：

[1] Macquarie Univ, Dept Elect, N Ryde, NSW 2109, Australia

来源：

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 | 1998年

关键词：

D O I：

10.1109/ASPDAC.1998.669493

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the architecture, design and implementation of a 16 point FFT processor for a high speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6 mu m TLM CMOS, operates worst case at 50 MHz at a supply voltage of 2.5 volts, and consumes 80 mW.

引用

页码：335 / 336

页数：2