Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing

被引：0

作者：

Tripathy, Suryasnata ^{[1
]}

Omprakash, L. B. ^{[1
]}

Mandal, Sushanta K. ^{[1
]}

Patro, B. S. ^{[1
]}

机构：

[1] KIIT Univ, Bhubaneswar 751024, Orissa, India

来源：

2015 INTERNATIONAL CONFERENCE ON COMMUNICATION, INFORMATION & COMPUTING TECHNOLOGY (ICCICT) | 2015年

关键词：

Vedic multiplier; Urdhva Tiryakbhyam; CMOS; High speed; Low power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Cadence EDA tool.

引用

页数：6

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