Low Cost At-Speed Testing using On-Product Clock Generation Compatible with Test Compression

被引：0

作者：

Keller, B. ^{[1
]}

Chakravadhanula, K. ^{[1
]}

Foutz, B. ^{[1
]}

Chickermane, V. ^{[1
]}

Malneedi, R. ^{[1
]}

Snethen, T. ^{[1
]}

Iyengar, V. ^{[2
]}

Lackey, D. ^{[2
]}

Grise, G. ^{[2
]}

机构：

[1] Cadence Design Syst, San Jose, CA USA

[2] IBM Corp, Burlington, VT 05405 USA

来源：

INTERNATIONAL TEST CONFERENCE 2010 | 2010年

关键词：

INSTRUCTION SET ARCHITECTURE; IMPLEMENTATION; CORE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuit's DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

引用

页数：10

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