Layout Optimization of Short De-embedding Structure for Accurate On-Chip Inductor Characterization

被引：1
作者：
Shafi, K. T. Muhammed [1 ]
Baipadi, Varuna [1 ]
Vanukuru, Venkata [1 ]
机构：
[1] GLOBALFOUNDRIES, Design Enablement Team, Bangalore, Karnataka, India
来源：
2021 IEEE 21ST TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF) | 2021年
关键词：
Characterization; de-embedding; layout optimization; on-chip inductor;
D O I：
10.1109/SiRF51851.2021.9383413
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A potentially significant limitation of typical short structure in de-embedding launch line inductance with groundsignal-ground (GSG) padsets is revealed in this paper. It is shown that the calculated inductance (L) value with conventional openshort-pad (OSP) de-embedding is significantly higher than the actual value. With the help of electro-magnetic (EM) simulations, the mechanism behind this inaccurate short de-embedding for L calculation is demonstrated. A simple alternative short structure is proposed to alleviate this issue. The proposed structure is extensively validated using well calibrated EM simulations across inductor geometries. Finally, measured result of spiral inductor with GSG padsets validate the merit of the proposed approach.
引用
收藏
页码：31 / 33
页数：3
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