Layout Optimization of Short De-embedding Structure for Accurate On-Chip Inductor Characterization

被引：1

作者：

Shafi, K. T. Muhammed ^{[1
]}

Baipadi, Varuna ^{[1
]}

Vanukuru, Venkata ^{[1
]}

机构：

[1] GLOBALFOUNDRIES, Design Enablement Team, Bangalore, Karnataka, India

来源：

2021 IEEE 21ST TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF) | 2021年

关键词：

Characterization; de-embedding; layout optimization; on-chip inductor;

D O I：

10.1109/SiRF51851.2021.9383413

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A potentially significant limitation of typical short structure in de-embedding launch line inductance with groundsignal-ground (GSG) padsets is revealed in this paper. It is shown that the calculated inductance (L) value with conventional openshort-pad (OSP) de-embedding is significantly higher than the actual value. With the help of electro-magnetic (EM) simulations, the mechanism behind this inaccurate short de-embedding for L calculation is demonstrated. A simple alternative short structure is proposed to alleviate this issue. The proposed structure is extensively validated using well calibrated EM simulations across inductor geometries. Finally, measured result of spiral inductor with GSG padsets validate the merit of the proposed approach.

引用

页码：31 / 33

页数：3

共 50 条

[1] New on-chip de-embedding for accurate evaluation of symmetric devices
Goto, Yosuke
Natsukari, Youhei
Fujishima, Minoru
JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (04) : 2812 - 2816
[2] Verification of transmission line de-embedding method for on-chip spiral inductor based on electromagnetic simulation
Han, Bo
Song, Youcai
Wang, Zhongxin
Li, Jun
Shi, Xiaofeng
INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2016, 29 (04) : 686 - 694
[3] A new on-wafer de-embedding technique for on-chip RF transmission line interconnect characterization
Tretiakov, Y
Rascoe, J
Vaed, K
Woods, W
Venkatadri, S
Zwick, T
ARFTG: AUTOMATIC RF TECHNIQUES GROUP, CONFERENCE DIGEST, SPRING 2004: ON WAFER CHARACTERIZATION, 2004, : 69 - 72
[4] Revised L-2L Method for On-Chip De-Embedding
Erickson, Nicholas
Achkir, Brice
Fan, Jun
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2019, 61 (01) : 209 - 216
[5] Advanced On-chip SOL Calibration Method for Unknown Fixture De-embedding
Yoon, Changwook
Chen, Bichen
Ye, Xiaoning
Fan, Jun
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17 (04) : 543 - 551
[6] A semi-distributed method for Inductor de-embedding
Dang, J.
Noculak, A.
Korndoerfer, F.
Jungemann, C.
Meinerzhagen, B.
2014 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS), 2014, : 141 - 145
[7] De-embedding transmission line measurements for accurate modeling of IC designs
Mangan, AM
Voinigescu, SP
Yang, MT
Tazlauanu, M
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (02) : 235 - 241
[8] De-embedding method for on-wafer RF CMOS inductor measurements
Drakaki, Maria
Hatzopoulos, Alkis A.
Siskos, Stylianos
MICROELECTRONICS JOURNAL, 2009, 40 (06) : 958 - 965
[9] Modeling of a Schottky diode in CMOS process with a flexible "open-through" on-chip de-embedding method
Sun X.
Zhang C.
Gao L.
Li Y.
Wang Z.
Tsinghua Science and Technology, 2011, 16 (02) : 175 - 180
[10] Modeling of a Schottky Diode in CMOS Process with a Flexible “Open-Through” On-Chip De-embedding Method
孙旭光
张春
高立力
李永明
王志华
Tsinghua Science and Technology, 2011, 16 (02) : 175 - 180

← 1 2 3 4 5 →