Generic description and synthesis of LDPC decoders

被引：25
作者：
Guilloud, Frederic
Boutillon, Emmanuel
Tousch, Jacky
Danger, Jean-Luc
机构：
[1] Ecole Natl Super Telecommun Bretagne, Dept Signal Commun, GET, Brest 3, France
[2] Univ Bretagne Sud, LESTER, Lorient, France
[3] TurboConcept SAS, Plouzane, France
[4] Ecole Natl Supr Telecommun, F-75013 Paris, France
来源：
IEEE TRANSACTIONS ON COMMUNICATIONS | 2007年 / 55卷 / 11期
关键词：
binary low-density parity-check (LDPC) codes; decoder implementation; iterative decoding; VLSI;
D O I：
10.1109/TCOMM.2007.908517
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for non-flooding schedules is also given.
引用
收藏
页码：2084 / 2091
页数：8
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