Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs

Cellular Automata (CA) circuits have received significant attention for efficient hardware implementation of Built-In Self-Test (BIST) structures or pseudorandom number generators (PRNGs). In this paper, we have presented an efficient automation technique of linear computational complexity, to generate design descriptions of high performance FPGA based scan path architectures for CA based circuits with inbuilt seeding and testability features without any hardware overhead. The designs have been described using target FPGA specific primitive instantiation and placement constraints to ensure regularity, cascadability and adjacency of the neighbouring CA cells. This approach realizes a well handcrafted design which outperforms similar circuit implementations described using higher levels of abstraction.