A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology

Shrinking of technology node in advanced VLSI devices and scaling of supply voltage degrade the performance characteristics and reduce the soft error resilience of modern downscaled digital circuits. In this paper, we propose a reliable near-threshold 7T SRAM cell with single ended read and differential write operations based on a previous proposed 5T cell. Our new cell improves read speed without degrading of write speed compared to the recently reported 7T cell. Furthermore, our proposed cell provides high soft error reliability amongst all the SRAM cells mentioned in this paper. We compared the performance and reliability characteristics of 5T, 6T, 8T and previous 7T cells with our new 7T SRAM cell to show its efficacy. The simulations are performed using HSPICE in 20 nm FinFET technology at V-DD = 0.5 V. The results show that the new 7T cell has high write speed, read and write margins with improved read speed and low leakage power in the hold "0" state compared to 5T cell. In addition, the study of performance parameters under process and environmental variations considering ageing effect in near-threshold region shows the robustness of the proposed 7T SRAM cell against these variations.