Room temperature Si δ-growth on Ge incorporating high-K dielectric for metal oxide semiconductor applications

被引：6
|
作者：
Hong, Augustin J. [1 ]
Ogawa, Masaaki [1 ]
Wang, Kang L. [1 ]
Wang, Yong [2 ,3 ]
Zou, Jin [2 ,3 ]
Xu, Zheng [4 ]
Yang, Yang [4 ]
机构：
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
[2] Univ Queensland, Sch Engn, Brisbane, Qld 4072, Australia
[3] Univ Queensland, Ctr Microscopy & Microanal, Brisbane, Qld 4072, Australia
[4] Univ Calif Los Angeles, Dept Mat Sci & Engn, Los Angeles, CA 90095 USA
来源：
APPLIED PHYSICS LETTERS | 2008年 / 93卷 / 02期
基金：
美国国家科学基金会; 澳大利亚研究理事会;
关键词：
D O I：
10.1063/1.2957476
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
A low temperature Al2O3/4 monolayer amorphous Si gate stack process was demonstrated on p-type Ge wafers using atomic layer deposition and molecular beam epitaxy. Multifrequency capacitance-voltage (C-V) and current-voltage (I-V) characteristics showed excellent electrical properties of the Pt/Al2O3/4 ML Si/Ge metal oxide semiconductor capacitor. No kinks from 1 MHz to 4 kHz and a leakage current density of 2.6 x 10(-6) A/cm(2) at 1 V with an equivalent oxide thickness of 2.5 nm. The interface characterization using a conductance method showed that interface trap density at the near midgap was 8 x 10(12) eV(-1) cm(-2) and a mean capture cross section of holes was extracted to be 10(-16) cm(2). (C) 2008 American Institute of Physics.
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页数：3
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