Threshold voltage in junctionless nanowire transistors

被引：104

作者：

Trevisoli, Renan Doria ^{[1
]}

Doria, Rodrigo Trevisoli ^{[2
]}

de Souza, Michelly ^{[2
]}

Pavanello, Marcelo Antonio ^{[1
,2
]}

机构：

[1] Univ Sao Paulo, LSI PSI USP, Lab Sistemas Integraveis, BR-05508010 Sao Paulo, Brazil

[2] Ctr Univ FEI, Dept Elect Engn, BR-09850901 Sao Bernardo Do Campo, Brazil

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2011年 / 26卷 / 10期

基金：

巴西圣保罗研究基金会;

关键词：

CONDUCTION MECHANISMS; MODEL; DEVICE;

D O I：

10.1088/0268-1242/26/10/105009

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage.

引用

页数：8

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