High-Parallel Architecture for H.264/AVC Intra Prediction Implemented via VLSI

The complicated calculations and data dependency have limited further application of the H.264/AVC standard for a considerable time. To solve such a problem, here in this paper, a dual-parallel architecture that combines block parallel processing and mode parallel processing is proposed to speed up the process. Since the improvement of the parallelism will lead to increased consumption of the hardware. a formula sharing method is presented to reduce the hardware cost. The experimental results have shown that, synthesized into a TSMC 0.18 mu m CMOS cell library, the new architecture only requires less than 135 K gates and is able to encode 1080pHD video sequences at 30 frames per second (fps), when running at 136 MHZ.