A high data-reuse architecture with double-slice processing for full-search block-matching algorithm

被引：0
作者：
Lai, YK
Chen, LF
机构：
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS | 2003年
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D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a high data-reuse architecture with double-slice processing for full-search block-matching algorithm is described. Based on double one-dimensional (I-D) processing element (PE) arrays and triple data interlacing shift-register arrays, the proposed architecture can efficiently reuse data not only in the overlapped region of the adjacent candidate block at the same slice but also in the overlapped region of the vertically adjacent candidate block slices to de crease external memory access and to save the pin counts. It also achieves 100% hardware utilization and high throughput with low memory bandwidth and complicated control overhead.
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页码：716 / 719
页数：4
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