A high data-reuse architecture with double-slice processing for full-search block-matching algorithm

In this paper, a high data-reuse architecture with double-slice processing for full-search block-matching algorithm is described. Based on double one-dimensional (I-D) processing element (PE) arrays and triple data interlacing shift-register arrays, the proposed architecture can efficiently reuse data not only in the overlapped region of the adjacent candidate block at the same slice but also in the overlapped region of the vertically adjacent candidate block slices to de crease external memory access and to save the pin counts. It also achieves 100% hardware utilization and high throughput with low memory bandwidth and complicated control overhead.