A Comparison of Fault-Tolerant Memories in SRAM-Based FPGAs

被引：0
作者：
Rollins, Nathaniel [1 ]
Fuller, Megan [1 ]
Wirthlin, Michael J. [1 ]
机构：
[1] Brigham Young Univ, NSF Ctr High Performance Reconfigurable Comp CHRE, Dept Elect & Comp Engn, Provo, UT 84602 USA
来源：
2010 IEEE AEROSPACE CONFERENCE PROCEEDINGS | 2010年
基金：
美国国家科学基金会;
关键词：
SYSTEMS; RELIABILITY;
D O I：
暂无
中图分类号：
V [航空、航天];
学科分类号：
08 ; 0825 ;
摘要：
This paper compares the effectiveness and cost of different fault-tolerant techniques for FPGA memories (BRAMs, LUTRAMs, and SRLs). TMR, parity with duplication, compliment duplicate (CD) with duplication, single-error correction/double-error detection (SEC/DED), and SEC/DED with duplication are the techniques used in this study to protect FPGA memories. Memory scrubbing is also added to each of these techniques. The effectiveness of each technique is measured by the number of sensitive bits in each design as well as the number of critical failures. A critical failure is defined as an upset whose effects can only be repaired through device reconfiguration. Cost is measured in terms of FPGA slices and BRAMs. This study finds that for BRAMs and LUTRAMs scrubbing with TMR provides the best protection. For SRLs scrubbing is unnecessary, and TMR provides the best protection. This study also provides a variety of reliability-area trade-off points with fault-tolerant techniques other than TMR.
引用
收藏
页数：12
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