250nA Quiescent current high PSRR voltage reference in standard CMOS process

被引：0

作者：

Strik, Sergei ^{[1
]}

Strik, Viktor ^{[1
]}

机构：

[1] Texas Instruments Inc, MDP MLP, Santa Clara, CA 95051 USA

来源：

2014 PROCEEDINGS OF THE 14TH BIENNIAL BALTIC ELECTRONICS CONFERENCE (BEC 2014) | 2014年

关键词：

PSSR; CMOS; LDO; power management; battery; battery management; analog; semiconductor;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Power efficiency is very important in portable devices as well as noise immunity of analog ICs. This article describes a voltage reference circuit that operates with extremely low quiescent current (below 250 nA) and is compatible with a standard CMOS process. It is optimally designed for a wide range of applications such as portable electronic devices, automotive, medical equipment, including system-on-chip (SoC) implementation where high-power supply rejection ratio (PSRR) and switching noise immunity are very important. The described voltage reference provides up to 90 dB at low frequencies. Standard deviation of the output voltage variation is 0.5% with a temperature coefficient of 15 ppm/degrees C at -40 degrees C to 125 degrees C temperature range. These characteristics are achievable at 1.6V to 5.5V supply voltage range. Various design approaches for input noise immunity of voltage reference are implemented.

引用

页码：45 / 48

页数：4