Design and FPGA implementation of digit-serial modified booth multipliers

This paper presents a comprehensive approach to the ASIC design of general digit-size digit-serial modified Booth multipliers, together with corresponding hardware implementations employing the Actel 1.2 mu FPGA technology. The proposed design is based on a decomposition of the N-bit multiplier and the M-bit multiplicand each into a unique set of D radix-2(D) components. The decomposed multiplicand components are then combined with the modified Booth encoded multiplier components to form the desired product. Analytical expressions are derived for the total number of gate-equivalents in the corresponding FPGA implementations in terms of D and N. Similarly, by using a critical path analysis, analytical expressions are derived for the maximum possible bit-clock rate in terms of D. These results are then combined to arrive at the efficiency of the implementation quantified by the throughput per unit area as a function of the digit-size D (with the wordlength L being taken as a parameter). It is shown that for wordlengths in the range 16 less than or equal to L less than or equal to 22, the digit-size falls somewhere in the range 3 less than or equal to D less than or equal to 8 for optimal throughput per unit area, where L = min{M, N}. Viewlogic simulation results are presented to verify the proposed digit-serial modified Booth multipliers.