Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

被引：19

作者：

Chao, Yue ^{[1
]}

Luong, Howard C. ^{[1
]}

Hong, Zhiliang ^{[2
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Hong Kong, Peoples R China

[2] Fudan Univ, Dept Microelect, Shanghai 200000, Peoples R China

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2015年 / 63卷 / 04期

关键词：

CMOS; frequency divider; millimeter-wave (mm-Wave); phase-locked loop (PLL); phase shifter; phased array; voltage-controlled oscillator (VCO);

D O I：

10.1109/TMTT.2015.2407364

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/-84 dBc/Hz at 100-kHz offset and -94/-88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 degrees range with an average resolution of 3.9 and amplitude variation less than +/- 0.1 dB, which makes it suitable for phased-array transceivers.

引用

页码：1193 / 1201

页数：9

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