Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

被引：27

作者：

Sachid, Angada B. ^{[1
]}

Lin, Hsiang-Yun ^{[1
,2
]}

Hu, Chenming ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[2] Taiwan Semicond Mfg Co, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 12期

关键词：

Corner spacer; nanowire FET; parasitic capacitance; FINFET; SOURCE/DRAIN; UNDERLAP; MOSFETS; DEVICES; DESIGN; NM;

D O I：

10.1109/TED.2017.2764511

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This problem is exacerbated with the introduction of multigate FETs such as FinFET and gate-all-around FETs. In this paper, we introduce the corner spacer design for gate-all-around nanowire FET to significantly decrease parasitic capacitance with negligible degradation in ON-current. We show that the parasitic capacitance of a well-engineered corner spacer in a nanowire FET can be reduced by over 80% compared to the device with full nitride spacers. Ring oscillator stage delay and energy consumption of the corner spacer design are lower than the full spacer by over 50% each. This paper shows the possibility of engineering the spacers as a performance booster to continue scaling.

引用

页码：5181 / 5187

页数：7

共 24 条

[1] [Anonymous], 2008, IEDM
[2] Auth C., 2012, 2012 IEEE Symposium on VLSI Technology, P131, DOI 10.1109/VLSIT.2012.6242496
[3] A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
Basker, V. S.
Standaert, T.
Kawasaki, H.
Yeh, C. -C.
Maitra, K.
Yamashita, T.
Faltermeier, J.
Adhikari, H.
Jagannathan, H.
Wang, J.
Sunamura, H.
Kanakasabapathy, S.
Schmitz, S.
Cummings, J.
Inada, A.
Lin, C. -H.
Kulkarni, P.
Zhu, Y.
Kuss, J.
Yamamoto, T.
Kumar, A.
Wahl, J.
Yagishita, A.
Edge, L. F.
Kim, R. H.
Mclellan, E.
Holmes, S. J.
Johnson, R. C.
Levin, T.
Demarest, J.
Hane, M.
Takayanagi, M.
Colburn, M.
Paruchuri, V. K.
Miller, R. J.
Bu, H.
Doris, B.
McHerron, D.
Leobandung, E.
O'Neill, J.
[J]. 2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 19 - +
[4] Cheng K., 2016, 2016 IEEE International Electron Devices Meeting (IEDM), p17.1.1, DOI 10.1109/IEDM.2016.7838436
[5] Colinge JP, 2008, INTEGR CIRCUIT SYST, P1, DOI 10.1007/978-0-387-71752-4_1
[6] Pragmatic design of nanoscale multi-gate CMOS
Fossum, JG
Wang, LQ
Yang, JW
Kim, SH
Trivedi, VP
[J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 613 - 616
[7] Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results
Granzner, R
Polyakov, VM
Schwierz, F
Kittler, M
Luyken, RJ
Rösner, W
Stådele, M
[J]. MICROELECTRONIC ENGINEERING, 2006, 83 (02) : 241 - 246
[8] Hisamoto D, 2000, IEEE T ELECTRON DEV, V47, P2320, DOI 10.1109/16.887014
[9] James D., 2012, P IEEE CUST INT CIRC, P1, DOI DOI 10.1109/CICC.2012.6330644.
[10] Extension and source/drain design for high-performance FinFET devices
Kedzierski, J
Ieong, M
Nowak, E
Kanarsky, TS
Zhang, Y
Roy, R
Boyd, D
Fried, D
Wong, HSP
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 952 - 958

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