A Delay-Locked Loop with Digital Background Calibration

被引：6

作者：

Lin, Wei-Ming ^{[1
]}

Teng, Kuang-Fu ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan

来源：

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2009年

关键词：

CHARGE PUMP;

D O I：

10.1109/ASSCC.2009.5357157

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18 mu m technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm(2).

引用

页码：317 / 320

页数：4

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