In order to guarantee reliability of semiconductor devices for automotive applications an optimized package design is required. Clearly the design must be based on the best choice of geometry, materials and manufacturing processes. It is well known that the various process steps involved during package manufacturing occur at relatively high temperatures. Consequently, due to the mismatch of thermal expansion coefficients of the package materials, high thermal stresses arise at operating temperatures and may lead to failure of the device. Typical device failure modes include delamination of material interfaces or bulk material fracture. In this paper we focus on the prediction of silicon fracture in the microchips of electronic devices. Due to their brittle nature the strength data of silicon dies will scatter and a probabilistic approach to failure is required. For this purpose Weibull theory will be used and combined with analytical as well as numerical tools in order to describe the state of stress in the package and in particular within the silicon die. As a result of the analysis the probability of fracture in a microchip can now be assessed and used for further quality assurance purposes. The paper will start with a brief introduction to Weibull theory and present the 3-Point-Bending (3PB) experiments that were used to obtain the Weibull parameters for characterization of a combination of surface and edge flaw induced silicon die fracture. Moreover, the ball-on-edge and ball-on-ring tests will be described and used to separately characterize edge or surface flaws, respectively. Particular emphasis will also be given to the transferability of Weibull probability results from one specimen configuration to another resulting in a change of surface size and stress. In this context it will be described how a stress distribution and, in particular, a multiaxial state of stress influences the variability in strength. Moreover it will be shown how the corresponding Weibull integrals can be implemented numerically and used for postprocessing of finite element results. The paper concludes by demonstrating how these procedures can be used for optimizing the design of a real silicon die package.
