Variable-length input Huffman coding for system-on-a-chip test

被引:125
作者
Gonciari, PT [1 ]
Al-Hashimi, BM
Nicolici, N
机构
[1] Univ Southampton, Elect Syst Design Grp, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England
[2] McMaster Univ, Computer Aides Design & Test Res Grp, Dept Elect & Comp Engn, Hamilton, ON L8S 4K1, Canada
关键词
automated test equipment (ATE); embedded core testing; system-onia-chip (SOC); test data compression; test resource partitioning; test set encoding; test time reduction;
D O I
10.1109/TCAD.2003.811451
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead, and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new variable-length input Huffman coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, when compared with three previous approaches [1]-[3], which reduce some test data compression environment's parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.
引用
收藏
页码:783 / 796
页数:14
相关论文
共 41 条
  • [11] ELMALEH S, 2001, P IEEE VLSI TEST S A, P114
  • [12] ERGLEZ F, 1989, P INT S CIRC SYST MA, P1929
  • [13] Test set compaction algorithms for combinational circuits
    Hamzaoglu, I
    Patel, JH
    [J]. 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 283 - 289
  • [14] High speed serializing/de-serializing design-for-test method for evaluating a 1GHz microprocessor
    Heidel, D
    Dhong, S
    Hofstee, P
    Immediato, M
    Nowka, K
    Silberman, J
    Stawiasz, K
    [J]. 16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1998, : 234 - 238
  • [15] Ichihara H., 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, P294, DOI 10.1109/ICVD.2000.812624
  • [16] Dynamic test compression using statistical coding
    Ichihara, H
    Ogawa, A
    Inoue, T
    Tamura, A
    [J]. 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 143 - 148
  • [17] COMPACT: A hybrid method for compressing test data
    Ishida, M
    Ha, DS
    Yamaguchi, T
    [J]. 16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1998, : 62 - 69
  • [18] Deterministic built-in pattern generation for sequential circuits
    Iyengar, V
    Chakrabarty, K
    Murray, BT
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 15 (1-2): : 97 - 114
  • [19] Scan vector compression/decompression using statistical coding
    Jas, A
    Ghosh-Dastidar, J
    Touba, NA
    [J]. 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 114 - 120
  • [20] Jas A., 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), P418, DOI 10.1109/ICCD.1999.808576